1. Field of the Invention
The present invention relates to a clock buffer and, more particularly, to a high-speed clock buffer that has a substantially reduced crowbar current.
2. Description of the Related Art
A clock buffer is a device that drives a clock signal onto a capacitive load such as, for example, a clock tree. Current generation clock trees, where a single clock signal drives a number of clock inputs, typically have a loading capacitance that ranges from approximately 10 pF to 100 pF, depending on the size of the system.
There are many applications, such as in communication networks, where the edge transitions of the clock signal are critical to the operation of the system. Thus, it is critical to those systems that the clock buffer has sufficient drive for the load which, in the case of a clock tree, can be substantial.
FIG. 1 shows a schematic diagram that illustrates a conventional clock buffer 100. As shown in FIG. 1, buffer 100 includes an inverter 110 and a driver inverter 120. Inverter 110 has an input and an output, while driver inverter 120 has an input that is connected to the output of inverter 110, and an output.
As shown in FIG. 1, driver inverter 120 includes a p-channel transistor P1 and an n-channel transistor N1. P-channel transistor P1 has a source connected to VCC (a power supply node), a drain, and a gate connected to the output of inverter 110. N-channel transistor N1 has a source connected to ground, a drain connected to the drain of transistor P1, and a gate connected to the output of inverter 110.
Transistors P1 and N1 are sized to provide sufficient drive to the load. As a result, transistors P1 and N1 are typically much larger than the transistors used to form inverter 110. In addition, as the capacitive loading (of the clock trees) increases, it is common practice to further increase the sizes of transistors P1 and N1 to provide the extra current drive.
In operation, inverter 110 receives a clock signal CLK, inverts the clock signal CLK, and outputs a first inverted clock signal CLK1. Driver inverter 120, in turn, receives the first inverted clock signal CLK1, inverts the clock signal CLK1, and outputs a second inverted clock signal CLK2. Buffer 100 is non-inverting because the input clock signal CLK and the second inverted clock signal CLK2 have the same logic state.
With respect to driver inverter 120, p-channel transistor P1 turns on and conducts when the source-to-drain voltage VSD is greater than zero (e.g., VSD greater than 0), and the gate-to-source voltage VGS is less than the threshold voltage VTP of the transistor (e.g., VGS less than VTP). N-channel transistor NI turns on and conducts when the drain-to-source voltage VDS is greater than zero (e.g., VDS greater than 0), and the gate-to-source voltage VGS is greater than the threshold voltage VTN of the transistor (e.g., VGS greater than VTN).
One of the advantages of buffer 100 is that when the voltages of the clock signal CLK and the first inverted clock signal CLK1 are at CMOS levels, no current is dissipated. For example, when the voltage of the first inverted clock signal CLK1 is at ground, p-channel transistor P1 is turned on and n-channel transistor N1 is turned off. Similarly, when the voltage of the first inverted clock signal CLK1 is at VCC, p-channel transistor PI is turned off and n-channel transistor N1 is turned on.
One of the disadvantages of buffer 100, however, is that transistors P1 and N1 of inverter 120 both turn on and conduct during a portion of the rising and falling edges of the inverted clock signal CLK1. (The transistors of inverter 110 also turn on and conduct during a portion of the rising and falling edges of the clock signal CLK, but since the transistors that make up inverter 110 are substantially smaller than transistors P1 and N1 the effect is much less significant.)
Although clock signals are typically depicted as instantaneously changing logic states (from a logic low to a logic high or vice versa), in actual practice a finite time, such as 100-200 pS, is required for the signal to change logic states, particularly if a relatively large capacitive load is present.
FIG. 2 shows a timing diagram that illustrates the first inverted clock signal CLK1 input to inverter 120. As shown in FIG. 2, clock signal CLK1 starts as a logic low voltage VL at time t0, and begins transitioning from a logic low to a logic high at time t1. At time t2, clock signal CLK passes a turn on voltage V1 for transistor N1 (equal to the threshold voltage VTN of transistor N1), and at time t3 passes a turn off voltage V2 for transistor P1 (where the gate-to-source voltage is greater than the threshold voltage VTP). Clock signal CLK1 then reaches a logic high voltage VH at time t4.
From time t0 to time t1, transistor P1 is turned on charging the load to a logic high, while transistor N1 is turned off. At time t2, however, the voltage on the gates of transistors P1 and N1 has risen to a point where the gate-to-source voltage (VGS) of transistor N1 is greater than the threshold voltage of transistor N1. As a result, transistor N1 turns on.
Thus, both transistors P1 and N1 remain turned on until clock signal CLK1 passes time t3 when the gate-to-source voltage (VGS) of transistor P1 is no longer less than the threshold voltage of transistor P1. This, in turn, causes transistor P1 to turn off. Thus, from time t2 to time t3 (about 80% of the rise time), both transistors P1 and N1 are turned on. A similar situation occurs on the falling edge of clock signal CLK1.
When transistors P1 and N1 are both turned on at the same time, a current ICB (see FIG. 1), known as a crowbar current, flows directly from transistor P1 to transistor N1. The crowbar current is an undesirable current because the crowbar current consumes power and slows down the response time of the circuit by increasing the rise and fall time of the clock signal CLK2.
The rise and fall times are increased because the crowbar current ICB that is sunk by transistor N1 is unavailable to charge the load on the falling edge of the clock signal CLK1, and limits the current that can be sunk from the load on the rising edge of the clock signal CLK1. By restricting the current that can be used to charge or discharge the load, the rise and fall times are necessarily increased. In addition, the crowbar current can cause supply and ground noise. Thus, there is a need for a driver inverter that substantially reduces the crowbar current.
The present invention substantially reduces the crowbar current in a driver inverter, which has a pair of complementary driver transistors, by adjusting the turn on and turn off times of the driver transistors such that each driver transistor turns on after the other driver transistor has turned off.
A buffer in accordance with the present invention includes a pull up block that receives an input signal which, in turn, has a plurality of edges. The pull up block outputs a first signal in response to the input signal a delay time after the input signal is received. The first signal beginning a transition from a first logic level to a second logic level at a first time.
The buffer also includes a first driver transistor that is connected to the pull up block and an output node. The first driver transistor receives the first signal, sources a first current to the output node when a voltage level of the first signal is in a first voltage range, and stops the first current when the voltage level of the first signal is in a second voltage range.
The buffer further includes a pull down block that is connected to the pull up block. The pull down block receives the input signal and outputs a second signal in response to the input signal a delay time after the input signal is received. The second signal beginning a transition from the first logic level to the second logic level at a second time. The second time being different from the first time.
The buffer additionally including a second driver transistor that is connected to the pull down block and the output node. The second driver transistor receives the second signal, sinks a second current from the output node when a voltage level of the second signal is in a first voltage range, and stopps the second current when the voltage level of the second signal is in a second voltage range.
A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed description and accompanying drawings that set forth an illustrative embodiment in which the principles of the invention are utilized.